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Si5040
5.8.1.1. Dynamic Register Control
The dynamic control of RxLoopFAcq (Register 98) is required to ensure the locking performance of the CDR. It is
required for all applications that RxLoopFAcq be set to 98h when RX LOL is asserted and to 00h when RX LOL is
deasserted. Only the default value and the value given above are supported for writes to Register 98. Any read
back of this register will not necessarily return the value written. If a valid reference clock is applied at pins 13,14
and rxRefclkEn = 1 (reg7[0]) and Rx VCOCAL = x0b (reg8[2:1]), then the dynamic register write to register 98 is
not necessary.
In addition, for proper LOL performance, RxPDGainAcq (Register 77) must be written once to 0Dh after power is
applied or a SW reset is implemented. If a valid reference clock is applied at pins 13,14 and rxRefclkEn = 1
(reg7[0]) and Rx VCOCAL = x0b (reg8[2:1]), then it is not necessary to write to register 77.
5.8.2. Frequency LOL
The Si5040 supports the use of a ~622 MHz or ~155 MHz (/64 or /16) reference clock. The reference clock
frequency is selected in the ChipConfig1 register (Register 2). There are two ways in which FREQLOL is selected.
When register7[3:2] = 10b, then FREQLOL is selected. When register7[3] = 0 and register7[1] = 1, then FREQLOL
is selected. LOL is asserted if the recovered clock frequency deviates from the reference clock frequency by
>±1000 ppm. LOL is de-asserted if the recovered clock is within ±200 ppm of the reference clock frequency. Refer
to Figure 14 for CDR and VCO behaviors upon declaring LOL.
5.8.3. Acquisition Time Enhancement
The acquisition lock time for a signal applied at RXDIN can be reduced to less than 15 ms by the following register
writes:
1. Write register 86 = 0011 1000 = 38h.
2. Write register 67 = 0100 0001 = 41h.
3. Write register 68 = 0000 0011 = 03h.
5.8.4. LOL Interrupt
LOL may be configured to generate an interrupt. The status of the LOL interrupt bit can be read from the
RxintStatus register (Register 5). The status of LOL may also be read from the RxAlarmStatus register (Register 9).
LOL may also be asserted upon activation of LOS (see "5.4. Receiver Loss of Signal Alarm (LOS)" on page 20 and
Figure 15 on page 26). Receive data (RD) may be squelched on LOL. This option is configured in the
RxdPathConfig register (Register 28).
Rev. 1.3
25
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